1. Field of the Invention
The present invention relates to a method of manufacturing a metal pattern of a semiconductor device, and more particularly, to a method of manufacturing a metal pattern of a semiconductor device which has improved stability and adhesiveness for subsequent processes.
2. Description of the Related Art
Semiconductor devices require high capacity and fast operating speeds to power today""s electronic devices. Accordingly, semiconductor device manufacturing methods continually strive to improve the integration density, reliability, and response times of the devices.
However, as the integration density increases and the overall size of the device itself decreases, limitations are encountered. For example, as the critical dimension of the device is reduced to sub-micron size or less in order to increase the integration density, the channel lengths, distances between active regions, sizes of via holes or studs, contact areas between metals, etc. are reduced. This causes various problems, such as short channel effect (SCE) or stability, with regard to a transistor for example. Also, problems concerning resistance, stability, or adhesiveness between layers are generated as the critical dimension of metal patterns is reduced. The stability or adhesiveness of the metal pattern may deteriorate during the implementing processes to form a metal pattern after depositing a metal, or due to an indirect influence of a subsequent process.
FIGS. 1A to 1D are schematic cross-sectional views illustrating the conventional method of manufacturing a metal pattern of a semiconductor device. Referring to FIG. 1A, an insulating layer 110 comprising silicon oxide is formed on a semiconductor substrate 100 having an impurity doped region 101. An opening 112 which exposes the impurity doped region 101 is formed in the insulating layer 110 by a photolithography process.
FIG. 1B illustrates the processes for forming a metal pattern. First, a Ti (titanium) layer 121 is formed by depositing Ti by a sputtering or a CVD method to a thickness about 30-500 xc3x85. The Ti layer 121 is formed to improve adhesiveness between a subsequently deposited metal material and the underlying silicon oxide layer. On the Ti layer 121, a TiN (titanium nitride) layer 122 is formed as a barrier layer to thickness of about 50-2000 xc3x85. The TiN layer 122 is formed to prevent an impregnation of a subsequently deposited metal material to form a metal layer contacting the underlying active region. Thereafter, a metal such as tungsten, aluminum, or the like is deposited to a thickness of about 300-8000 xc3x85 to form a metal layer 123, and an SiN (silicon nitride) layer 124 is then deposited on metal layer 123.
The SiN layer 124 is formed by depositing SiN using a low pressure chemical vapor deposition (LPCVD) method. The LPCVD is a deposition method for forming thin films using a chemical reaction by employing heat energy in a reaction vessel where the pressure is maintained at about 200-700 torr. The LPCVD is performed by heat-treating at about 400-600xc2x0 C. with a mixed gas of SiH4 and N2, or a mixed gas of SiH4 and N2O as source gases. With this method, the uniformity and step coverage of the resulting film is good and a large number of wafers can be processed at once.
Referring to FIG. 1C, an anisotropic etching from the upper layer is implemented by using a photoresist pattern 130 as an etching mask to form a desired pattern. Beneath the photoresist pattern 130, an SiN pattern 124a, a metal layer pattern 123a, a TiN pattern 122a and a Ti pattern 121a are successively formed. The SiN pattern 124a formed on the metal layer pattern 123a functions as an anti-reflective layer during a subsequent photolithography process, and it also reinforces shoulders of SiN spacers formed on both sidewalls of the metal pattern. After implementing this etching, note that sidewalls of each pattern (Ti pattern sidewalls 121b, TiN pattern sidewalls 122b, metal layer pattern sidewalls 123b, and SiN pattern sidewalls 124b) are exposed.
Referring to FIG. 1D, the photoresist pattern 130 is removed and SiN is deposited on the thus obtained pattern. An etch back process is implemented to form SiN spacers 125 on side walls of the patterns to prevent an oxidation of a metal, and to implement a self aligned contact hole (SAC) process to manufacture a metal pattern 120. The LPCVD deposition parameters for forming the SiN spacers 125 are the same as those for the SiN layer 124.
The SAC process is briefly explained as follows. Present semiconductor devices have a design rule of 0.15 xcexcm or less, and accordingly, the critical dimension is reduced and contact holes must be formed in even thicker interlayer dielectric layers. As a result, it becomes difficult to maintain the process margins during the formation of the contact hole, and in order to ensure the process margin, spacers are formed on the side walls of the pattern. Essentially, the spacer secures the process margin and is called a shoulder margin.
During the manufacturing process of the metal pattern, the following factors may influence the characteristics of the metal layer.
A defect may be generated by a thermal budget on the metal layer during the spacer forming process after forming the metal pattern. Also, the thermal budget may generate gases from layers surrounding the metal layer, such as an insulating layer. The gases, for example, oxygen, humidity, etc., can function as oxidizing agents and potentially oxidize surrounding exposed metal, especially an exposed portion of the Ti pattern which has a high reactivity. If so, the adhesiveness and the stability of the metal pattern is reduced. If a subsequent metal layer pattern having a strong stress characteristic is formed on the oxidized Ti pattern, a separation of a portion of the Ti layer can be induced if the applied stress is larger than a critical value at an edge portion of the Ti pattern.
FIG. 2 illustrates graphs obtained by detecting amounts of gases generated from an insulating layer during a heat treatment for the formation of a subsequent layer. In FIG. 2, xe2x80x98axe2x80x99 corresponds to H2O gas and xe2x80x98bxe2x80x99 corresponds to O2 gas when the insulating layer (silicon oxide layer) is formed and as the subsequent layer (SiN layer) is formed. FIG. 2 confirms that an appreciable amount of oxidizing gases are generated during the heat treatment. The gas generated from one wafer does not induce considerable problem; however, when a process is implemented for about ten wafers simultaneously, the proportional increase in gas generated might induce a lifting of the metal pattern.
In order to solve the above-mentioned problem, various methods have been suggested. U.S. Pat. Nos. 5,310,456 and 5,314,576, both issued to Kadomura, disclose a process for protecting side walls of a metal pattern by using a protecting layer. However, this method costs a great deal, is inefficient, and is difficult to implement in a practical way.
U.S. Pat. No. 5,705,428, issued to Liu et al., discloses a method of forming a nitride layer on side walls of a metal pattern by injecting additional N2 gas during a typical etching process. However, the additional injected N2 gas produces undesirable polymer residues, and the etching efficiency and etching ratio are reduced. Furthermore, a high vacuum environment is required during the etching when utilizing some types of equipment, but the addition of N2 gas deteriorates the etching.
In another method, H2O is added during an ashing process using oxygen to form a metal oxide at an edge portion of the metal layer. However, the oxide compound is not uniformly formed, but is partially formed depending on the type of the metal, the grain sizes of the metal, and the quality of the interface of the metal. Accordingly, the control of the formation of the oxide layer is difficult and sometimes this oxide layer weakens the adhesiveness of the metal.
It is an object of the present invention to provide an advantageous method of manufacturing a metal pattern of a semiconductor device having improved stability and adhesiveness by solving the above-mentioned problems during the manufacturing thereof.
To accomplish this object, a method of manufacturing a metal pattern of a semiconductor device is provided. First, a Ti layer and a metal layer are successively formed on a semiconductor substrate or on an insulating layer. Then, a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning the Ti layer and the metal layer. An exposed portion of the Ti layer pattern forms TiN as a main product by implementing a heat treatment process under an atmosphere of a compound including nitrogen.
There is also provided a method of manufacturing a metal pattern of a semiconductor device including the following steps. A Ti layer and a metal layer are formed on a semiconductor substrate or an insulating layer. Then, a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning the Ti layer and the metal layer. Then, a metal nitride layer is formed by depositing metal nitride on the wiring pattern. A metal nitride pattern is formed on side walls of the Ti layer pattern and the metal layer pattern by etching the metal nitride layer.
In the present invention, an exposed portion of a Ti layer, which has high reactivity and induces various problems while implementing other processes, is treated by a compound including nitrogen in advance to form a nitride layer to protect the Ti layer, and therefore, the various problems associated with the exposed Ti layer can be overcome.